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| CY2CC810 1:10 Clock Fanout Buffer Features * * * * * * * * * * * * Low-voltage operation VDD range from 2.5V to 3.3V 1:10 fanout Over voltage tolerant input hot swappable Drives either a 50-Ohm or 75-Ohm transmission line Low-input capacitance 250 ps typical output-to-output skew 19 ps typical DJ jitter Typical propagation delay < 3.5 ns High-speed operation > 500 MHz Industrial versions available Available packages include: SOIC, SSOP Description The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic and buffers. The Cypress CY2CC810 fanout buffer features one input and ten outputs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. AVCMOS-type outputs dynamically adjust for variable impedance matching and reduce noise overall. . Block Diagram Q1 Q2 Pin Configuration IN GND Q1 VDD Q2 GND Q3 VDD Q4 GND CY2CC810 VD D Q3 Q4 Q5 Q6 Q7 IN INPUT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 GND Q8 Q9 Q 10 OUTPUT (AVCMOS) 20 pin SOIC/SSOP Pin Description Pin Number 1 2, 6, 10, 13, 17 4, 8, 15, 20 3, 5, 7, 9, 11, 12, 14, 16, 18, 19 Pin Name IN GND Input Ground Power Supply Output Description LVCMOS Power Power AVCMOS VDD Q1... Q10 Cypress Semiconductor Corporation Document #: 38-07056 Rev. *E * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 5, 2006 CY2CC810 Absolute Maximum Conditions[1, 2] Parameter VDD VIN VOUT TS TA VDD Ground Supply voltage Input Supply Voltage to Ground Potential Output Supply Voltage to Ground Potential Temperature, Storage Temperature, Operating Ambient Power Dissipation Description Min. -0.5 -0.5 -0.5 -65 -40 0.75 Max. 4.6 5.8 VDD +1 150 85 Unit V V V C C W DC Electrical Characteristics @ 3.3V (see Figure 5) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V VDD = Min., VIN = VIH or VIL VIN = 2.7V VIN = 0.5V IOH = -12 mA IOL = 12 mA Min. 2.3 2 Typ. 3.3 0.2 Max. 0.5 5.8 0.8 1 -1 20 Unit V V V V A A A V mA A mV -0.7 -1.2 -50 100 80 DC Electrical Characteristics @ 2.5V (see Figure 1) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = -18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V VIN = 2.4V VIN = 0.5V IOH = -7 mA IOH = 12 mA IOL = 12 mA Min. 1.8 1.6 Typ. Max. Unit V V 0.65 1.6 5.0 0.8 1 -1 20 -0.7 -1.2 -50 100 80 V V V A A A V mA A mV Capacitance Parameter Cin Cout Description Input Capacitance Output Capacitance VIN = 0V VOUT = 0V Test Conditions Min. Typ. 2.5 6.5 Max. Unit pF pF Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07056 Rev. *E Page 2 of 9 CY2CC810 Power Supply Characteristics (see Figure 5) Parameter ICC ICCD IC Description Delta ICC Quiescent Power Supply Current Dynamic Power Supply Current Test Conditions (IDD @ VDD = Max. and VIN = VDD) - (IDD @ VDD = Max. and VIN = VDD - 0.6V) VDD = Max. Input toggling 50% Duty Cycle, Outputs Open Min. Typ. Max. 50 0.63 25 Unit A mA/ MHz mA Total Power Supply Current VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ Power-up time for all VDDs Power-up to reach minimum specified voltage (power ramp must be monotonic) 0.05 tPU 500 ms High-frequency Parametrics Parameter DJ Description Jitter, Deterministic Test Conditions 50% duty cycle tW(50-50) The "point to point load circuit" Output Jitter - Input Jitter 50% duty cycle tW(50-50) Standard Load Circuit. 50% duty cycle tW(50-50) The "point to point load circuit" Fmax(2.5V Fmax(20) Maximum frequency VDD = 2.5 V Maximum frequency VDD = 3.3 V Maximum frequency VDD = 2.5 V tW Minimum pulse VDD = 3.3 V Minimum pulse VDD = 2.5 V The "point to point load circuit" VIN = 2.4V/0.0V VOUT = 1.7V/0.7V 20% duty cycle tW(20-80) The "point to point load circuit" VIN = 3.0V/0.0V VOUT = 2.3V/0.4V The "point to point load circuit" VIN = 2.4V/0.0V VOUT = 1.7V/0.7V The "point to point load circuit" VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V The "point to point load circuit" VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V 2.5V 3.3V See Figure 5 See Figure 7 See Figure 7 See Figure 7 Min. Typ. 23 19 Max. 35 30 160 650 200 250 MHz MHz Unit ps ps MHz Fmax(3.3V) Maximum frequency VDD = 3.3V See Figure 3 See Figure 7 1 200 MHz ns See Figure 3 1 AC Switching Characteristics @ 3.3V, VDD = 3.3V 5%, Temperature = -40C to +85C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) See Figure 10 Pulse Skew: Skew between opposite transitions of the same output See Figure 9 (tPHL - tPLH). Package Skew: Skew between outputs of different packages at the See Figure 11 same power supply voltage, temperature and package type. Description See Figure 4 Min. 1.5 1.5 Typ. 2.7 2.7 0.8 0.8 0.25 0.38 0.2 0.42 Max. Unit 3.5 3.5 ns ns V/ns V/ns ns ns ns Document #: 38-07056 Rev. *E Page 3 of 9 CY2CC810 AC Switching Characteristics @ 2.5V, VDD = 2.5V 5%, Temperature = -40C to +85C Parameter tPLH tPHL tR tF tSK(0) tSK(p) tSK(t) Propagation Delay - Low to High Propagation Delay - High to Low Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) See Figure 10 Pulse Skew: Skew between opposite transitions of the same output See Figure 9 (tPHL - tPLH). Package Skew: Skew between outputs of different packages at the See Figure 11 same power supply voltage, temperature and package type. Description See Figure 4 Min. 1.5 1.5 Typ. 2.0 2.0 0.8 0.8 0.25 0.38 0.4 0.65 Max. Unit 3.5 3.5 ns ns V/ns V/ns ns ns ns Parameter Measurement Information: VDD @ 2.5V Figure 1. Load Circuit [3,4,5] f F r o m O u tp u t U nder T est C L = 50 pF 500 ohm Figure 2. Voltage Waveforms Pulse Duration[6] t w(50-50) Input 1.25 V t w(20-80) Input 1.25 V 1.25 V 2.0 V 0V 2.0 V 0V Figure 3. Point to Point Load Circuit[3,4,5] F ro m O u tp u t U nder T est C L = 3 pF 500 ohm Notes 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50W, tR < 2.5 nS, tF < 2.5 nS. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd.. Document #: 38-07056 Rev. *E Page 4 of 9 CY2CC810 Figure 4. Voltage WaveformsPropagation Delay Times[4] 2.0 V 0V tPHL 1.25 V VOH 1.25 V VOL Input tPLH Output 1.25 V 1.25 V Parameter Measurement Information: VDD @ 3.3V Figure 5. Load Circuit [3,4,5] From Output Under Test C L = 50 pF 500 ohm Figure 6. Voltage Waveforms-Pulse Duration[6] tw(50-50) Input 1.5V t w(20-80) Input 1.5V 1.5V 2.7V 0V 2.7V 0V Figure 7. Point to Point Load Circuit[3,4,5] From Output Under Test CL = 3 pF 500 ohm Figure 8. Voltage Waveforms Propagation Delay Times[4] 2.7V 0V tPHL 1.5V 1.5V VOH VOL Input tPLH Output 1.5V 1.5V Document #: 38-07056 Rev. *E Page 5 of 9 CY2CC810 Figure 9. Pulse Skew-tsk(p) 3V 1.5V INPUT t PLH t PHL 0V VOH 1.5V OUTPUT tsk (P) = VOL l tPHL - tPLH l Figure 10. Output Skew-tsk(0) 3V 1 .5 V IN P U T tP LH 1 tP H L 1 0V VOH 1 .5 V OUTPUT 1 ts k ( O ) ts k ( O ) VOL VOH 1 .5 V OUTPUT 2 VOL tP L H 2 tP L H 2 ts k ( P ) = l tP LH 2 - tP LH 1 l o r tP H L2 - tP H L1 l Figure 11. Package Skew-tsk(t) 3V 1.5V INPUT tPLH1 tPHL1 0V VOH 1.5V PACKAGE 1 OUTPUT tsk (t) tsk (t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tPLH 2 tsk (t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Document #: 38-07056 Rev. *E Page 6 of 9 CY2CC810 Ordering Information Part Number CY2CC810OI CY2CC810OIT CY2CC810OC CY2CC810OCT Lead-free CY2CC810OXC CY2CC810OXCT CY2CC810OXI CY2CC810OXIT Package Type 20-pin SSOP 20-pin SSOP-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel 20-pin SSOP 20-pin SSOP-Tape and Reel Product Flow Industrial, -40C to 85C Industrial, -40C to 85C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C Package Drawing and Dimensions Figure 12. 20-Lead (300-Mil) SOIC S20.3/SZ20.3 NOTE : PIN 1 ID 10 1 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.391] 0.300[7.620] MIN. MAX. 4. PACKAGE WEIGHT 0.55gms * 0.394[10.007] 0.419[10.642] 11 20 0.026[0.660] 0.032[0.812] PART # S20.3 STANDARD PKG. SZ20.3 LEAD FREE PKG. 0.497[12.623] 0.513[13.030] SEATING PLANE 0.092[2.336] 0.105[2.667] * 0.050[1.270] TYP. 0.013[0.330] 0.019[0.482] 0.004[0.101] 0.0118[0.299] 0.004[0.101] 0.015[0.381] 0.050[1.270] * 0.0091[0.231] 0.0125[0.317] 51-85024-*C Document #: 38-07056 Rev. *E Page 7 of 9 CY2CC810 Figure 13. 20-lead (5.3-mm) Shrunk Small Outline Package O20 51-85077-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07056 Rev. *E Page 8 of 9 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2CC810 Document History Page Document Title: CY2CC810 1:10 Clock Fanout Buffer Document #: 38-07056 REV. ** *A *B ECN NO. 107081 114315 119117 Issue Date 06/07/01 05/09/02 10/07/02 Orig. of Change IKA TSM RGL IDD Validation Added 5.8 as the Max. value of VIH in the DC Electrical Characteristics @3.3V table. Changed the Max. value of VIH from 1.8 to 5.0 in the DC Electrical Characteristics @2.5V table. Added power up requirements to maximum ratings information. Added typical values Updated jitter and skew specs. Removed devices with SOIC package Added Lead-free SSOP package Added tpu parameter in the Power Supply Characteristics table Description of Change Convert from IMI to Cypress *C *D 122743 387761 12/14/02 See ECN RBI RGL *E 499991 See ECN RGL Document #: 38-07056 Rev. *E Page 9 of 9 |
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